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Description
Frequency synthesizers are widely used in many applications. For instance, particle physics experiments such as the LHC operate at a 40 MHz system clock, while the proposed CEPC is expected to use 43.3 MHz. To accommodate such diverse requirements, a wide-range frequency synthesizer with flexible reference and synthesized clocks is essential. We present a phase-locked loop (PLL) based on a ring-oscillator voltage-controlled oscillator (VCO) fabricated in a 55 nm technology. The PLL comprises a phase detector (PD), a programmable charge pump (CP), a low-pass filter (LPF), a ring-oscillator voltage-controlled oscillator (ROVCO), buffers, dividers, and selectors.
Three versions of the VCO core have been implemented to compare clock performance. Each VCO core includes three delay cells and an output buffer. VCO1 features a single tuning band spanning 0.4 to 4.45 GHz. VCO2 employs a 3-bit control to divide the total range into eight sub-bands. VCO3 utilizes a combined tuning method, generating 16 sub-bands with a slightly narrower frequency range of 1.4 to 4.1 GHz. The use of sub-bands reduces the VCO gain (Kvco), with the maximum value decreasing from 6.46 GHz/V for VCO1 to 0.52~2.88 GHz/V for VCO2, and further to 0.81~1.12 GHz/V for VCO3. The phase noise varies from -105 to -96 dBc/Hz at 1-MHz offset, depending on the frequency. Additionally, selecting appropriate sub-bands ensures that the control voltage remains within an optimal operating range when the PLL locks to the target frequency.
The design employs a programmable pre-divider (M={1,2}), feedback divider (X=4×{2,3,…31}) and output divider (K={1,2}×{2,4,8,16}×{1,3,5,15}) to enable a broad frequency range. The final output frequency is determined by the equation: Fout=Fref[X/(MK)]. To accommodate the broad tuning range and diverse division factors, the loop bandwidth is programmable through adjustments to the charging current and LPF resistance, ensuring proper loop bandwidth and phase margin are maintained. Preliminary laboratory tests confirm correct functionality and performance, with comprehensive testing, including X-ray characterization, scheduled for completion in September. Detailed design and measurements will be presented.
