A 5~36 ps Event-Driven Vernier Time-to-Digital Converter in 55-nm CMOS

16 Nov 2025, 17:30
10m
2F, Activities Center (Academia Sinica)

2F, Activities Center

Academia Sinica

128 Section 2, Academia Road, Nankang, Taipei 115201, Taiwan
POSTER ASICs ALL Poster

Speakers

Hui Jiang (IHEP) Xiongbo Yan (IHEP)

Description

High resolution time-to-digital converter (TDC) is widely used in high-energy physics experiments, TOF-PET, and other fields. Targeting next-generation photon detectors (MCP-PMT, SiPM), this work presents a TDC prototype design achieving state-of-the-art time resolution in a 55-nm CMOS process.

The design integrates two timing cores for independent time-of-arrival (TOA) and time over threshold (TOT) measurements. Each core has four primary components: two ring oscillators (VRO) based on a vernier structure, a controller, a quantization block and counters. The VRO includes a slow ring (X-chain) and a fast ring (Y-chain), both employing 15 delay units. Each delay unit adopts a voltage-controlled starved-current-mirror NAND gate. The time resolution is determined by the difference between the unit delays of the X chain and Y chain.

The TDC employs event-driven logic to reduce power consumption. Upon event detection, the controller segments the pulse into START and STOP signals to enable both VRO rings. The SR-latch array in the quantization block synchronously captures phases states across all NAND outputs, comparing each rising and falling edges. Measurement terminates when X-chain and Y-chain phase align, latching the corresponding 30-bit thermometer code. The VRO enters low-power standby mode after quantization until reactivated by subsequent events. A 10-bit coarse counter and a 10-bit fine counter provide a dynamic range of 2.4 μs. Finally, the two cores generate 100-bit raw data, which is serialized and transmitted through a serializer working at 640 MHz.

The post-layout simulations demonstrate a fitting resolution of 1.77 ps under typical condition. The differential nonlinearity (DNL) and integral nonlinearity (INL) is within ±1 LSB and ±2 LSB, respectively. The TDC consumes 8 mW during active operation and 0.72 mW in standby mode after event completion. Preliminary tests confirm correct operation of the VRO rings with achievable time resolution ranging from 5 ps to 36 ps. Additional testing is currently underway, with results to be reported subsequently.

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