Speaker
Description
The ALICE experiment will upgrade the innermost three layers of its vertexing detector, the Inner Tracking System (ITS), during the next LHC Long Shutdown (LS3) with a novel, bent, ultra-light MAPS-based tracker. Six wafer-scale sensor chips will be bent into three cylinders, held in place only by carbon foam, leaving no material except for the silicon die in most of the ALICE central barrel acceptance. Two prototype ASICs, approximately $25.8\,\mathrm{cm}$ called MOSS (MOnolithic Stitched Sensor) and MOST (MOnolithic Stitched sensor with Timing), have been produced. These two chips follow complementary approaches to evaluate the use of stitched CMOS sensors for the first time in an HEP experiment.
In particular, MOSS employs a less dense integration, exploring the feasibility of stitched power and signal distribution, as well as front-end qualification. MOST, on the other hand, pushed more towards the density limits, qualifying power domain segmentation using power switches to detach regions with production failures.
This contribution will give an overview of various results from powering tests, functional studies, pixel matrix characterization, and in-beam tests of both test structures. The yield of MOSS is estimated to be approximately $90\%$. This number takes into account powering, as well as functional aspects such as digital and analog pulsing, where a fraction of observed failures is caused by the test chip architecture. Disregarding these failures, the yield of the final ITS3 sensor ASIC will be achieved up to $>98\%$.
Furthermore, it was shown that MOSS can operate with $>99\%$ efficiency and $<10^{-6}\,\mathrm{pixel}^{-1}\,\mathrm{event}^{-1}$ fake-hit rate up to $400\,\mathrm{krad}$ TID and $4\cdot 10^{12}\,1\,\mathrm{MeV}\,\mathrm{n}_\mathrm{eq}\,\mathrm{cm}^{-2}$ NIEL.
This presentation will highlight the most recent results of power testing, functional testing, and matrix characterization of the prototype chips and their implications towards the final ITS3 ASIC design.
