A Low-Noise Analog Front-End Readout ASIC for High-Rate Applications in Pixel Detectors

16 Nov 2025, 11:00
10m
2F, Activities Center (Academia Sinica)

2F, Activities Center

Academia Sinica

128 Section 2, Academia Road, Nankang, Taipei 115201, Taiwan
POSTER ASICs ALL Poster

Speaker

Chunlai Dong

Description

This paper presents the design and implementation of an analog front-end readout chip tailored for silicon pixel detectors, aiming to meet the requirements of energy extraction and signal shaping under high event rate particle detection scenarios. Fabricated using the GSMC 130\si{\nano\metre} CMOS process, the chip integrates key functional modules including a charge-sensitive amplifier (CSA), a CR-CR shaper, an inverting amplifier, a peak holder, and an analog multiplexer. The CSA converts transient charge signals generated by incident particles into voltage signals proportional to the deposited energy, providing the initial signal amplification and conversion. The CR-CR shaper performs signal filtering and shaping, producing a pulse width of approximately 10 $\mu\mathrm{s}$. The inverting amplifier adjusts the signal polarity and amplitude, while the peak holder captures and retains the pulse maximum. A 4:1 multiplexer enables selection of CSA, shaper, inverter, or peak output for monitoring. The measurement results show that the chip exhibits good linearity and stable shaping performance in the dynamic range of 0-20ke$^-$. Under typical operating conditions, the chip consumes 20.8 mW of power and achieves an equivalent noise charge (ENC) of approximately 25.2e$^-$. The core circuit occupies an area of approximately 44\si{\micro\metre} $\times$ 46\si{\micro\metre}. These features endow the chip with superior energy resolution and dynamic range, making it suitable for front-end analog readout in high-resolution silicon pixel arrays, and applicable to integrated nuclear detection systems and X-ray polarization measurement missions.

Author

Co-author

Prof. Dong Wang (Central China Normal University)

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